Chemin:OKDatasheet > Fiche de Semi-conducteurs > Lattice Datasheet > M5LV-128/104-7VI
M5LV-128/104-7VI spec: 7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
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M5LV-128/104-7VI Datasheet et spécifications
Fabricant : Lattice
Emballage : TQFP
Pins : 100
Température : Min -40 °C | Max 85 °C
Taille : 1126 KB
Application : 7ns fifth generation MACH architecture CPLD (Complex Programmable Logic Device)
M5LV-128/104-7VI PDF Download